[all-commits] [llvm/llvm-project] 175850: [AArch64][SVE2] Combine trunc+add+lsr to rshrnb

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 175850f98726b543f9a1f5309d5fded481e60efa
      https://github.com/llvm/llvm-project/commit/175850f98726b543f9a1f5309d5fded481e60efa
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll

  Log Message:
  -----------
  [AArch64][SVE2] Combine trunc+add+lsr to rshrnb

The example sequence

  add z0.h, z0.h, #32
  lsr z0.h, #6
  st1b z0.h, x1

can be replaced with

  rshrnb z0.b, #6
  st1b z0.h, x1

As the top half of the destination elements are truncated.

In similar fashion,

  add z0.s, z0.s, #32
  lsr z1.s, z1.s, #6
  add z1.s, z1.s, #32
  lsr z0.s, z0.s, #6
  uzp1 z0.h, z0.h, z1.h

Can be replaced with

  rshrnb z1.h, z1.s, #6
  rshrnb z0.h, z0.s, #6
  uzp1 z0.h, z0.h, z1.h

Differential Revision: https://reviews.llvm.org/D155299