[all-commits] [llvm/llvm-project] c3cfbb: [GlobalISel] Add dead flags to implicit defs in ISel

Pierre van Houtryve via All-commits all-commits at lists.llvm.org
Wed Aug 9 05:21:08 PDT 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c3cfbbc4160c3e0284034c98b332b468328458e3
      https://github.com/llvm/llvm-project/commit/c3cfbbc4160c3e0284034c98b332b468328458e3
  Author: pvanhout <pierre.vanhoutryve at amd.com>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
    M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
    M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
    M llvm/test/CodeGen/X86/GlobalISel/mul-scalar.ll
    M llvm/test/CodeGen/X86/GlobalISel/select-add.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-undef.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
    M llvm/utils/TableGen/GlobalISelEmitter.cpp
    M llvm/utils/TableGen/GlobalISelMatchTable.cpp
    M llvm/utils/TableGen/GlobalISelMatchTable.h

  Log Message:
  -----------
  [GlobalISel] Add dead flags to implicit defs in ISel

Checks for implicit defs that are unused within a pattern and mark them as dead.

This is done directly at the TableGen level forr efficiency.
The instructions are directly created with the "dead" operand and no further analysis is needed later.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D157273

More information about the All-commits mailing list