[all-commits] [llvm/llvm-project] 44383a: [RISCV] Add fixed vector tests for ct[l, t]z_zero_u...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 44383ac7fdbb16fea048f60d8009599b9bf7d793
      https://github.com/llvm/llvm-project/commit/44383ac7fdbb16fea048f60d8009599b9bf7d793
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-08 (Tue, 08 Aug 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

  Log Message:
  -----------
  [RISCV] Add fixed vector tests for ct[l,t]z_zero_undef

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157293


  Commit: 768740ef7727fe892de269092509c55c0723b05f
      https://github.com/llvm/llvm-project/commit/768740ef7727fe892de269092509c55c0723b05f
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-08 (Tue, 08 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

  Log Message:
  -----------
  [RISCV] Lower unary zvbb ops for fixed vectors

This reuses the same strategy for fixed vectors as other ops, i.e. custom lower
to a scalable *_vl SD node.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157294


  Commit: 5d510ea72426791e44017d5cd7b83c4bb716a6b7
      https://github.com/llvm/llvm-project/commit/5d510ea72426791e44017d5cd7b83c4bb716a6b7
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-08-08 (Tue, 08 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

  Log Message:
  -----------
  [RISCV] Lower vro{l,r} for fixed vectors

We need to add new VL nodes to mirror ISD::ROTL and ISD::ROTR.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157295


Compare: https://github.com/llvm/llvm-project/compare/e2851ad43d3e...5d510ea72426