[all-commits] [llvm/llvm-project] 3bcfd6: [RISCV][GlobalISel] Legalize logical instructions ...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bcfd6e96203bbfc5a71f3476a96548d82107a18
      https://github.com/llvm/llvm-project/commit/3bcfd6e96203bbfc5a71f3476a96548d82107a18
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-08-07 (Mon, 07 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir

  Log Message:
  -----------
  [RISCV][GlobalISel] Legalize logical instructions for nonpow 2 types

Legalize G_AND, G_OR, G_XOR for (s7, s48) on rv32 and (s15, s72) on rv64

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D157017