[all-commits] [llvm/llvm-project] 649e1d: [RISCV][GlobalISel] Legalize bitshift instructions...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 649e1d1b9de9d03918691e8dd3700f8d077d3498
      https://github.com/llvm/llvm-project/commit/649e1d1b9de9d03918691e8dd3700f8d077d3498
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-08-07 (Mon, 07 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir

  Log Message:
  -----------
  [RISCV][GlobalISel] Legalize bitshift instructions for narrow types

Legalize G_SHL, G_ASHR and G_LSHR for types narrower and upto (and including) XLen: (i7, i8,
i16 and i32) for rv32 and (i8, i15, i16, i32 and i64) for rv64. This requires
adding some rules to handle G_ANYEXT, G_ZEXT and G_SEXT.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155772