[all-commits] [llvm/llvm-project] 8ff264: Revert "[CodeGen]Allow targets to use target speci...

Alex Bradbury via All-commits all-commits at lists.llvm.org
Mon Aug 7 08:29:57 PDT 2023 

  Branch: refs/heads/release/17.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ff26437cfd37a3611d3b6066e5aa2cf933887e0
      https://github.com/llvm/llvm-project/commit/8ff26437cfd37a3611d3b6066e5aa2cf933887e0
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2023-08-07 (Mon, 07 Aug 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LiveRangeEdit.cpp
    M llvm/lib/CodeGen/LiveRangeShrink.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/lib/CodeGen/SplitKit.h
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    R llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
    M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
    M llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
    M llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
    M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
    M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
    M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
    M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
    M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
    R llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
    M llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
    M llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
    M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
    M llvm/test/CodeGen/AMDGPU/nested-calls.ll
    M llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
    M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
    R llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
    M llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    R llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    R llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
    M llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    R llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
    R llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
    M llvm/test/CodeGen/Mips/madd-msub.ll
    M llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
    M llvm/test/CodeGen/X86/dagcombine-cse.ll
    M llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll

  Log Message:
  -----------
  Revert "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"

And dependent commits.

Details in D150388.

This reverts commit 825b7f0ca5f2211ec3c93139f98d1e24048c225c.
This reverts commit 7a98f084c4d121244ef7286bc6503b6a181d446e.
This reverts commit b4a62b1fa546312d882fa12dfdcd015177d66826.
This reverts commit b7836d856206ec39509d42529f958c920368166b.

No conflicts in the code, few tests had conflicts in autogenerated CHECKs:
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll

Reviewed By: alexfh

Differential Revision: https://reviews.llvm.org/D156381

(cherry picked from commit a496c8be6e638ae58bb45f13113dbe3a4b7b23fd)


  Commit: 99ed472f29ebea183b6e512c6f8a0ef98cee698b
      https://github.com/llvm/llvm-project/commit/99ed472f29ebea183b6e512c6f8a0ef98cee698b
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2023-08-07 (Mon, 07 Aug 2023)

  Changed paths:
    M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
    M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
    M llvm/test/Transforms/MemCpyOpt/callslot.ll
    M llvm/test/Transforms/MemCpyOpt/stack-move.ll

  Log Message:
  -----------
  Revert "Reapply: [MemCpyOpt] implement single BB stack-move optimization which unify the static unescaped allocas"""

Breaks Asan and LTO.

This reverts commit ea72b5137eb72391ad192dbb01084c21b9fe8b71.

(cherry picked from commit 00653889883f2d818536efcb21c6c8b739f0888b)


  Commit: 2f40e7b2bf59e5dbf557ab2943f3ea574dd2eaae
      https://github.com/llvm/llvm-project/commit/2f40e7b2bf59e5dbf557ab2943f3ea574dd2eaae
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-08-07 (Mon, 07 Aug 2023)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/CodeGen/ABIInfoImpl.cpp
    M clang/lib/CodeGen/ABIInfoImpl.h
    M clang/lib/CodeGen/Targets/RISCV.cpp
    M clang/test/CodeGen/RISCV/abi-empty-structs.c

  Log Message:
  -----------
  [clang][RISCV] Fix bug in ABI handling of empty structs with hard FP calling conventions in C++

As reported in <https://github.com/llvm/llvm-project/issues/58929>,
Clang's handling of empty structs in the case of small structs that may
be eligible to be passed using the hard FP calling convention doesn't
match g++. In general, C++ record fields are never empty unless
[[no_unique_address]] is used, but the RISC-V FP ABI overrides this.

After this patch, fields of structs that contain empty records will be
ignored, even in C++, when considering eligibility for the FP calling
convention ('flattening'). It isn't explicitly noted in the RISC-V
psABI, but arrays of empty records will disqualify a struct for
consideration of using the FP calling convention in g++. This patch
matches that behaviour. The psABI issue
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/358> seeks
to clarify this.

This patch was previously committed but reverted after a bug was found.
This recommit adds additional logic to prevent that bug (adding an extra
check for when a candidate from detectFPCCEligibleStructHelper may not
be valid).

Differential Revision: https://reviews.llvm.org/D142327


Compare: https://github.com/llvm/llvm-project/compare/34cf263e6149...2f40e7b2bf59

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