[all-commits] [llvm/llvm-project] 7f9b94: [X86] LowerBuildVectorv16i8 - attempt to merge low...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f9b94c0445d92e44ee97d5300ac1657570f7bd9
      https://github.com/llvm/llvm-project/commit/7f9b94c0445d92e44ee97d5300ac1657570f7bd9
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-08-03 (Thu, 03 Aug 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/buildvec-insertvec.ll
    M llvm/test/CodeGen/X86/extract-concat.ll
    M llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll
    M llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll
    M llvm/test/CodeGen/X86/promote-vec3.ll

  Log Message:
  -----------
  [X86] LowerBuildVectorv16i8 - attempt to merge lowest 2 x i16 insertions into a i32 MOVD scalar_to_vectpr

Similar to D156350, if we were going to create 2 x i16 insertions (MOVD+PINSRW), try to merge them into a single MOVD to reduce the amount of GPR<->VEC traffic


  Commit: 4dcf6877b4bf1f72ff2326869d27a48287502758
      https://github.com/llvm/llvm-project/commit/4dcf6877b4bf1f72ff2326869d27a48287502758
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-08-03 (Thu, 03 Aug 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [X86] combineAnd - limit and(extract_vector_elt(shuffle(x)) -> extract_vector_elt(shuffle'(x)) fold to one use of the extract_vector_elt.

Prevents a regression in an upcoming patch.


Compare: https://github.com/llvm/llvm-project/compare/c4bb3e073548...4dcf6877b4bf