[all-commits] [llvm/llvm-project] 65a6be: [mlir][ArmSME] Use memref indices for load and store

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65a6be5de97adec09534d37019e384e374069ce7
      https://github.com/llvm/llvm-project/commit/65a6be5de97adec09534d37019e384e374069ce7
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2023-08-03 (Thu, 03 Aug 2023)

  Changed paths:
    M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
    M mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
    M mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Use memref indices for load and store

This patch extends the ArmSME load and store op lowering to use the
memref indices. An integration test that loads two 32-bit element ZA
tiles from memory and stores them back to memory in reverse order to
verify this is added.

Depends on D156467 D156558

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D156689