[all-commits] [llvm/llvm-project] 37ef64: [llvm-exegesis] Prevent llvm-exegesis from using u...

[Pavel Kosov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 37ef64078553af3e8d305ac2a5d50faa82f8b8bb
      https://github.com/llvm/llvm-project/commit/37ef64078553af3e8d305ac2a5d50faa82f8b8bb
  Author: Pavel Kosov <kpdev42 at gmail.com>
  Date:   2023-08-02 (Wed, 02 Aug 2023)

  Changed paths:
    M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
    M llvm/tools/llvm-exegesis/lib/Mips/Target.cpp
    M llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp
    M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
    M llvm/tools/llvm-exegesis/lib/Target.cpp
    M llvm/tools/llvm-exegesis/lib/Target.h
    M llvm/tools/llvm-exegesis/lib/X86/Target.cpp
    M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
    M llvm/utils/TableGen/InstrInfoEmitter.cpp

  Log Message:
  -----------
  [llvm-exegesis] Prevent llvm-exegesis from using unsupported opcodes

When generating snippets for AArch64 with --opcode-index=-1, the code
generator asserts on opcodes that are not supported according to CPU
features.

The same assertion can be triggered even when generating a serial
snippet for a supported opcode if SERIAL_VIA_NON_MEMORY_INSTR execution
mode is used and an unsupported instruction is chosen as the "other
instruction". Unlike the first case, this one may result in flaky
failures because the other instruction is randomly chosen from the
instructions suitable for serializing execution.

This patch adjusts TableGen emitter for *GenInstrInfo.inc to make
possible to query for opcode availability instead of just asserting on
unsupported ones.

~~

Huawei RRI, OS Lab

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D146303