[all-commits] [llvm/llvm-project] 1e86ab: [RISCVRVVInitUndef] Ignore tied use for partial un...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1e86abc914bbac9d825471444005da729e78cf43
      https://github.com/llvm/llvm-project/commit/1e86abc914bbac9d825471444005da729e78cf43
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-08-01 (Tue, 01 Aug 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  [RISCVRVVInitUndef] Ignore tied use for partial undef register

The purpose of this code is to restrict overlap between source and destination registers. The tied input register is conceptually part of the destination. I can't see any reason why we need to prevent a partial undef tied source here, and skipping it reduces register pressure slightly.

Differential Revision: https://reviews.llvm.org/D156709