[all-commits] [llvm/llvm-project] 9d927d: [mlir][Linalg] Add an end-to-end test for scalable...

[Andrzej Warzyński via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d927d039728edb9a4c26d9f5eeaa9becda89600
      https://github.com/llvm/llvm-project/commit/9d927d039728edb9a4c26d9f5eeaa9becda89600
  Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
  Date:   2023-08-01 (Tue, 01 Aug 2023)

  Changed paths:
    A mlir/test/Integration/Dialect/Linalg/CPU/Scalable/fill-1d.mlir
    A mlir/test/Integration/Dialect/Linalg/CPU/Scalable/lit.local.cfg

  Log Message:
  -----------
  [mlir][Linalg] Add an end-to-end test for scalable vectorisation

This patch adds our first integration test for scalable vectorisation in
Linalg. It simply runs `linalg.fill` to fill a scalable vector with a
pre-defined f32 value. The result is printed to stdout.

Note that with scalable architectures, the vector size is not know at
compile time, but it is known at runtime. For this reason, the length of
the output generated by the new test depends on the hardware implementation. For
Arm's SVE we do know that there will be at least 4 f32 elements in every
scalable vector register. CHECK lines were designed accordingly.

In order to see what happens for different implementations of SVE, you
can use the following QEMU settings:
  * qemu-aarch64 -cpu max,sve128=on
  * qemu-aarch64 -cpu max,sve512=on

ATM, this test is only enabled when `MLIR_RUN_ARM_SVE_TESTS` is set.

Differential Revision: https://reviews.llvm.org/D155839