[all-commits] [llvm/llvm-project] f92dc1: [RISCV] Add a common base class for RVInstI variat...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f92dc1083285f682ba9a858b8566823e6e449f6a
      https://github.com/llvm/llvm-project/commit/f92dc1083285f682ba9a858b8566823e6e449f6a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-31 (Mon, 31 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

  Log Message:
  -----------
  [RISCV] Add a common base class for RVInstI variations. NFC

We have multiple variations of InstrFormatI that pack different
fields into the upper 12 bits. The other 20 bits are all the same.

Add base class to capture this commonality and allow subclasses to
explicitly define Inst{31-20}.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156589


  Commit: fb97316ba0f613841604c484c9c7782ba8e2a12d
      https://github.com/llvm/llvm-project/commit/fb97316ba0f613841604c484c9c7782ba8e2a12d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-31 (Mon, 31 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  [RISCV] Add a common base class for RVInstR variations. NFC

We have multiple variations of InstrFormatR that pack different
fields into the upper 7 bits. The other 25 bits are all the same.

Add base class to capture this commonality and allow subclasses to
explicitly define Inst{31-25}.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156590


Compare: https://github.com/llvm/llvm-project/compare/5fbee1c6e300...fb97316ba0f6