[all-commits] [llvm/llvm-project] b7408e: [RISCV] Use x0 in vsetvli when avl is equal to vlmax.

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b7408ebbb7d8c5cd2a4883cb3fceb70ecfb3d6f4
      https://github.com/llvm/llvm-project/commit/b7408ebbb7d8c5cd2a4883cb3fceb70ecfb3d6f4
  Author: Jianjian GUAN <jacquesguan at me.com>
  Date:   2023-07-31 (Mon, 31 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll

  Log Message:
  -----------
  [RISCV] Use x0 in vsetvli when avl is equal to vlmax.

We could use x0 form in vsetvli when we already know the vlmax and avl is equal to it.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D156404