[all-commits] [llvm/llvm-project] afb9c0: [RISCV] Add support for XCVbi extension in CV32E40P

[melonedo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: afb9c04a5a44e62f945cd2f667706ded9facd8e3
      https://github.com/llvm/llvm-project/commit/afb9c04a5a44e62f945cd2f667706ded9facd8e3
  Author: melonedo <funanzeng at gmail.com>
  Date:   2023-07-28 (Fri, 28 Jul 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/corev/XCVbi-invalid.s
    A llvm/test/MC/RISCV/corev/XCVbi.s

  Log Message:
  -----------
   [RISCV] Add support for XCVbi extension in CV32E40P

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.

bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412