[all-commits] [llvm/llvm-project] 3c0604: [RISCV] Add support for XCVsimd extension in CV32E40P

[melonedo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3c0604b224e3c38b8db67d55320a0423bb4e8f49
      https://github.com/llvm/llvm-project/commit/3c0604b224e3c38b8db67d55320a0423bb4e8f49
  Author: melonedo <funanzeng at gmail.com>
  Date:   2023-07-28 (Fri, 28 Jul 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
    A llvm/test/MC/RISCV/corev/XCVsimd.s

  Log Message:
  -----------
  [RISCV] Add support for XCVsimd extension in CV32E40P

Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153721