[all-commits] [llvm/llvm-project] a81e1f: [RISCV] When using vror.vi for left rotate, mask t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a81e1f0fb29f4596825972fc856392dbacf455aa
      https://github.com/llvm/llvm-project/commit/a81e1f0fb29f4596825972fc856392dbacf455aa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-27 (Thu, 27 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

  Log Message:
  -----------
  [RISCV] When using vror.vi for left rotate, mask the inverted immediate to SEW.

This makes the assembly more readable.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D156348