[all-commits] [llvm/llvm-project] 5775db: [TableGen][RegisterInfoEmitter] Make entries of ba...

[Ivan Kosarev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5775db2e7b624365d68e5593415cde09c2a3c97c
      https://github.com/llvm/llvm-project/commit/5775db2e7b624365d68e5593415cde09c2a3c97c
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2023-07-27 (Thu, 27 Jul 2023)

  Changed paths:
    M llvm/test/TableGen/RegisterInfoEmitter-BaseClassOrder.td
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][RegisterInfoEmitter] Make entries of base register class tables human-readable.

Helps tracking changes in the tables on adding new register classes and
updating BaseClassOrder values.

Also eliminates tables translating base register class indexes into
TargetRegisterClass pointers.

Reviewed By: critson

Differential Revision: https://reviews.llvm.org/D156097