[all-commits] [llvm/llvm-project] baa338: [GlobalISel] GIntrinsic subclass to represent intr...

[Sameer Sahasrabuddhe via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: baa3386edb11a2f9bcadda8cf58d56f3707c39fa
      https://github.com/llvm/llvm-project/commit/baa3386edb11a2f9bcadda8cf58d56f3707c39fa
  Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
  Date:   2023-07-27 (Thu, 27 Jul 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.cpp

  Log Message:
  -----------
  [GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556