[all-commits] [llvm/llvm-project] 7c652f: [RISCV] Add tests for vnsrl.vx where shift amount ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c652feb95d7806a249f84540d23c62a828d438d
      https://github.com/llvm/llvm-project/commit/7c652feb95d7806a249f84540d23c62a828d438d
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-26 (Wed, 26 Jul 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add tests for vnsrl.vx where shift amount is truncated

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155927


  Commit: ce8f094da8b2224b46e4f7192502d38a28f6aabd
      https://github.com/llvm/llvm-project/commit/ce8f094da8b2224b46e4f7192502d38a28f6aabd
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-26 (Wed, 26 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add patterns for vnsrl.vx where shift amount is truncated

Similar to D155698 where the shift amount is extended, this patch extends the
ComplexPattern to handle the case where the shift amount has been truncated.
Truncations are custom lowered to truncate_vector_vl, and in cases like i64 ->
i16 they are truncated by one power of two at a time, so we need to unravel
nested layers of them.

The pattern can also be reused for Zvbb's vwsll.vx in an upcoming patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155928


  Commit: 33a93a41df260f6853ee6103b5b159b87544559c
      https://github.com/llvm/llvm-project/commit/33a93a41df260f6853ee6103b5b159b87544559c
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-26 (Wed, 26 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    A llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add SDNode patterns for vwsll.[vv,vx,vi]

This reuses the patterns introduced to help lower vnsr[a,l].vx in D155698.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155936


Compare: https://github.com/llvm/llvm-project/compare/e85fd3cbdd68...33a93a41df26