[all-commits] [llvm/llvm-project] 12832c: [RISCV] Add isAllocatable=0 to VCSR register class.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 12832c1773f520563601c85bd1163fc3e734d3e6
      https://github.com/llvm/llvm-project/commit/12832c1773f520563601c85bd1163fc3e734d3e6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-25 (Tue, 25 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Add isAllocatable=0 to VCSR register class.

This avoids creating an unnecessary register pressure set.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156196