[all-commits] [llvm/llvm-project] 74445d: [SVE] Add vselect(mla/mls) patterns for cases wher...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74445d652da99a1b622fccf18591811c016ceb4f
      https://github.com/llvm/llvm-project/commit/74445d652da99a1b622fccf18591811c016ceb4f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2023-07-25 (Tue, 25 Jul 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll

  Log Message:
  -----------
  [SVE] Add vselect(mla/mls) patterns for cases where a multiplicand is used for the false lanes.

Differential Revision: https://reviews.llvm.org/D155972