[all-commits] [llvm/llvm-project] 0e30ca: [AArch64] Extra testing for vselect(fmin/max patte...
David Green via All-commits
all-commits at lists.llvm.org
Mon Jul 24 06:55:54 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 0e30ca2ec9e4bbdf67d12a3e5b12eab644410aa4
https://github.com/llvm/llvm-project/commit/0e30ca2ec9e4bbdf67d12a3e5b12eab644410aa4
Author: David Green <david.green at arm.com>
Date: 2023-07-24 (Mon, 24 Jul 2023)
Changed paths:
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
Log Message:
-----------
[AArch64] Extra testing for vselect(fmin/max patterns. NFC
See D155872.
Commit: c3c8f0025a996db52f636492569f1c34ba2758d1
https://github.com/llvm/llvm-project/commit/c3c8f0025a996db52f636492569f1c34ba2758d1
Author: David Green <david.green at arm.com>
Date: 2023-07-24 (Mon, 24 Jul 2023)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
Log Message:
-----------
[AArch64] Add vselect(fmin/fmax) SVE patterns
For both minnum/maxnum and minimum/maximum, this adds tablegen patterns for
vselect(fmin/fmax), creating a predicate fminnm/fmaxnm/fmin/fmax nodes.
Differential Revision: https://reviews.llvm.org/D155872
Compare: https://github.com/llvm/llvm-project/compare/de3f7f01fe65...c3c8f0025a99
More information about the All-commits
mailing list