[all-commits] [llvm/llvm-project] 78d91d: [RISCV] Support register allocation for GHC when f...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78d91df452d669570e120cb5c3d5febf7f17475d
      https://github.com/llvm/llvm-project/commit/78d91df452d669570e120cb5c3d5febf7f17475d
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-23 (Sun, 23 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll

  Log Message:
  -----------
  [RISCV] Support register allocation for GHC when f/d is not specified in the architecture

This patch supports register allocation for floating-point types when
`zfinx` and `zdinx` is specified in the architecture for the GHC
calling convention.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155910