[all-commits] [llvm/llvm-project] c48ed9: [AMDGPU] Add llvm.amdgcn.wave.reduce.umin/umax Int...

[Pravin Jagtap via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c48ed93cf8c9db04ce72acf669dce396cc68672a
      https://github.com/llvm/llvm-project/commit/c48ed93cf8c9db04ce72acf669dce396cc68672a
  Author: Pravin Jagtap <Pravin.Jagtap at amd.com>
  Date:   2023-07-24 (Mon, 24 Jul 2023)

  Changed paths:
    M llvm/docs/AMDGPUUsage.rst
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umax.mir
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.reduce.umin.mir

  Log Message:
  -----------
  [AMDGPU] Add llvm.amdgcn.wave.reduce.umin/umax Intrinsic.

When input to intrinsic is uniform value, reduced value is
same as input whereas if input value is divergent we need
to iterate over all active lanes of WaveFront to perform
the reduction.

The control flow for a `loop` has been set up, which
iterates over `only` active lanes to perform reduction.

Introduced WAVE_REDUCE_UMIN_PSEUDO_U32 and
WAVE_REDUCE_UMAX_PSEUDO_U32 Pseudos which
are lowered Post-ISel (in `EmitInstrWithCustomInserter `).

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D154858