[all-commits] [llvm/llvm-project] f375ee: [RISCV] Add codegen for Zfbfmin instructions

[joshua-arch1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f375ee36c4e1c87b8ed47ef44d3613bd5756f57a
      https://github.com/llvm/llvm-project/commit/f375ee36c4e1c87b8ed47ef44d3613bd5756f57a
  Author: Jun Sha (Joshua) <cooper.joshua at linux.alibaba.com>
  Date:   2023-07-24 (Mon, 24 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    A llvm/test/CodeGen/RISCV/zfbfmin.ll

  Log Message:
  -----------
  [RISCV] Add codegen for Zfbfmin instructions

The implementation in https://reviews.llvm.org/D151313 is done for the circumstance without Zfbfmin. This patch adds codegen support for the 6 instructions provided in Zfbfmin extension.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153234