[all-commits] [llvm/llvm-project] 495bdf: [AArch64] Lower fcvtl2 (fpext) via tablegen patterns.

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 495bdfc7bb729ba22cf2b51d749f7789b0c2d9af
      https://github.com/llvm/llvm-project/commit/495bdfc7bb729ba22cf2b51d749f7789b0c2d9af
  Author: David Green <david.green at arm.com>
  Date:   2023-07-23 (Sun, 23 Jul 2023)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/Target.td
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
    M llvm/test/CodeGen/AArch64/fpext.ll

  Log Message:
  -----------
  [AArch64] Lower fcvtl2 (fpext) via tablegen patterns.

This patch does two things. First it removes the tryHighFPExt DAG2DAG method
used to select fcvtl2 instructions, using tablegen patterns through
SelectExtractHigh instead. This essentially undoes D71515, in a way that should
hopefully avoid any regressions. The second is that a GI equivalent of
SelectExtractHigh is added in selectExtractHigh, from G_UNMERGE_VALUES. The
end result is that GlobalISel (and some constrained fpext) can now make use of
the fcvtl2 instructions, saving an extra dup/ext.

Differential Revision: https://reviews.llvm.org/D155871