[all-commits] [llvm/llvm-project] ae6070: [DAG] SimplifyDemandedBits - call ComputeKnownBits...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ae60706da07a128e318ebc383d682e3861337c68
      https://github.com/llvm/llvm-project/commit/ae60706da07a128e318ebc383d682e3861337c68
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-21 (Fri, 21 Jul 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/X86/combine-srl.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - call ComputeKnownBits for constant non-uniform ISD::SRL shift amounts

We only attempted to determine KnownBits for uniform constant shift amounts, but ComputeKnownBits is able to handle some non-uniform cases as well that we can use as a fallback.