[all-commits] [llvm/llvm-project] 33a83c: [RISCV] Add SDNode patterns for vrol.[vv, vx] and v...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 33a83c5486d599e00f4c6ba35b12c1e74bc0554b
      https://github.com/llvm/llvm-project/commit/33a83c5486d599e00f4c6ba35b12c1e74bc0554b
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-21 (Fri, 21 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    A llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    A llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

These correspond to ROTL/ROTR nodes

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155439