[all-commits] [llvm/llvm-project] 418e67: [RISCV] Add tests for vnsr[l, a].wx patterns that c...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 418e678ba3b4bbe3433f5fcd94959ffa82a917a8
      https://github.com/llvm/llvm-project/commit/418e678ba3b4bbe3433f5fcd94959ffa82a917a8
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-21 (Fri, 21 Jul 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add tests for vnsr[l,a].wx patterns that could be matched

These patterns of ([l,a]shr v, ([s,z]ext splat)) only pick up the cases where
the scalar has the same type as the vector element. However since only the low
log2(SEW) bits of the scalar are read, we could use any scalar type that has
been extended.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155697


  Commit: 24628a14c4fb63eab8d5e68fb5c3cc49d14c0dcf
      https://github.com/llvm/llvm-project/commit/24628a14c4fb63eab8d5e68fb5c3cc49d14c0dcf
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-21 (Fri, 21 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

  Log Message:
  -----------
  [RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type than vector element

We're currently only matching scalar shift amounts where the type is the same
as the vector element type. But because only the bottom log2(2*SEW) bits are
used, only 7 bits will be used at most so we can use any scalar type >= i8.

This patch adds patterns for the case above, as well as for when the shift
amount type is the same as the widened element type and doesn't need extended.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155698


  Commit: f6bdfb0b92690403ceef8c1d58adf7a3a733b543
      https://github.com/llvm/llvm-project/commit/f6bdfb0b92690403ceef8c1d58adf7a3a733b543
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-21 (Fri, 21 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Remove VPatBinaryExtVL_WV_WX multiclass. NFC

It's no longer needed now that the sext/zext patterns have been merged.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155815


Compare: https://github.com/llvm/llvm-project/compare/a0eee6c97187...f6bdfb0b9269