[all-commits] [llvm/llvm-project] 48a749: [RISCV] Don't include X1 in the X0_PD register pair

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 48a749e26e6fc8596b31602b2696b91547246dcb
      https://github.com/llvm/llvm-project/commit/48a749e26e6fc8596b31602b2696b91547246dcb
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-07-20 (Thu, 20 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Don't include X1 in the X0_PD register pair

Zdinx on RV32 defines the D instructions as taking even register pairs,
and specifies that if using X0 when as a destination then X1 won't be
written, and if using X0 as a source then the value is still all 0s
(i.e. X1 isn't read). Therefore, it's incorrect to model X0_PD as having
X1 as a subregister. This will also be the case for register pairs in
Zacas and the P extension (and this patch takes the same approach as
D95588 does).

This patch introduces a dummy register that is solely used as a subreg
alongside X0 in X0_PD. An earlier version of the patch had a minor
effect on register allocation in some tests, which is now avoided by:
1) Adding RISCV::DUMMY_REG_PAIR_WITH_X0 to RISCVRegisterInfo::getReservedRegs
2) Defining a new register class that includes DUMMY_REG_PAIR_WITH_X0

Differential Revision: https://reviews.llvm.org/D153974