[all-commits] [llvm/llvm-project] f1cc79: [X86] Add test case showing incorrect and(sextinre...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1cc7913f3bfbb288ef44645a432aeac80dbf139
      https://github.com/llvm/llvm-project/commit/f1cc7913f3bfbb288ef44645a432aeac80dbf139
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-20 (Thu, 20 Jul 2023)

  Changed paths:
    A llvm/test/CodeGen/X86/scalar-ext-logic.ll

  Log Message:
  -----------
  [X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i2) fold


  Commit: 697f60598ec303efc0e9b092af1dbea2c46ebc56
      https://github.com/llvm/llvm-project/commit/697f60598ec303efc0e9b092af1dbea2c46ebc56
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-20 (Thu, 20 Jul 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/scalar-ext-logic.ll

  Log Message:
  -----------
  [DAG] hoistLogicOpWithSameOpcodeHands - ensure SIGN_EXTEND_INREG nodes have the same extension value type

Fix bug in the check for matching SIGN_EXTEND_INREG types


Compare: https://github.com/llvm/llvm-project/compare/2e0bf67df143...697f60598ec3