[all-commits] [llvm/llvm-project] c1013a: [X86][AArch64] Add additional extract_lowbits test

[Danila Malyutin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c1013a6eee0ca9ebbfda03fcfdb3afb42ebf31ff
      https://github.com/llvm/llvm-project/commit/c1013a6eee0ca9ebbfda03fcfdb3afb42ebf31ff
  Author: Danila Malyutin <dmalyutin at azul.com>
  Date:   2023-07-20 (Thu, 20 Jul 2023)

  Changed paths:
    M llvm/test/CodeGen/AArch64/extract-lowbits.ll
    M llvm/test/CodeGen/X86/extract-lowbits.ll

  Log Message:
  -----------
  [X86][AArch64] Add additional extract_lowbits test

Check that vreg_width-1 mask is only removed for shifts

Differential Revision: https://reviews.llvm.org/D155734


  Commit: 76fd79b9d537c5589f4e26dd7f5660d3c69d397a
      https://github.com/llvm/llvm-project/commit/76fd79b9d537c5589f4e26dd7f5660d3c69d397a
  Author: Danila Malyutin <dmalyutin at azul.com>
  Date:   2023-07-20 (Thu, 20 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/test/CodeGen/X86/extract-bits.ll
    M llvm/test/CodeGen/X86/extract-lowbits.ll

  Log Message:
  -----------
  [X86] Recognize standalone `(1 << nbits) - 1` pattern as bzhi

This can be thought as a subcase of `x & ((1 << nbits) - 1)` where x == -1

Differential Revision: https://reviews.llvm.org/D155622


Compare: https://github.com/llvm/llvm-project/compare/12baf9859b70...76fd79b9d537