[all-commits] [llvm/llvm-project] 80e20c: [RISCV] Add DAG combine for CTTZ/CTLZ in the case ...

[Djordje Todorovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80e20c8a8d074cd4053d9dbfd675025a28240c85
      https://github.com/llvm/llvm-project/commit/80e20c8a8d074cd4053d9dbfd675025a28240c85
  Author: Djordje Todorovic <djolertrk at gmail.com>
  Date:   2023-07-19 (Wed, 19 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine for CTTZ/CTLZ in the case of input 0

Within the AggressiveInstCombine Pass we have
an analysis/optimization that matches that
pattern of the Table Based CTZ. Some Targets do
not support/define ctz(0), but since the
AggressiveInstCombine is just an extension of
InstCombine, it should be a target-independent
canonicalization Pass, and therefore, we decided
to introduce several instructions, such as select
and compare that produce canonical IR, even if
the input is 0. The task for the Targets that do
support that input is to handle such a case and
to produce an optimal assembly.

This patch optimizes the CTTZ/CTLZ instructions
if the input is 0 by performing the`DAG combine`,
by generating the cttz(x) & 0x1f pattern (the
same goes for ctlz as well).

Differential Revision: https://reviews.llvm.org/D151449