[all-commits] [llvm/llvm-project] 32c257: [RISCV] Use the stack for MVT::f16 for fastcc when...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32c257d384f3f073b52b8779a5193cb190a4cae4
      https://github.com/llvm/llvm-project/commit/32c257d384f3f073b52b8779a5193cb190a4cae4
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-07-18 (Tue, 18 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll

  Log Message:
  -----------
  [RISCV] Use the stack for MVT::f16 for fastcc when there are no other registers available

In D155502, we added code for the compiler to check GPR-s for f16
under zhinx. This commit adds code to hit the stack when we run out of
GPR-s.

With this patch and D155502, resolves #63922

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155507