[all-commits] [llvm/llvm-project] ea3683: [RISCV] Improve type promotion for i32 clmulr/clmu...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea3683e98f107622ce54fa3d4c1457f4d597f808
      https://github.com/llvm/llvm-project/commit/ea3683e98f107622ce54fa3d4c1457f4d597f808
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-18 (Tue, 18 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll

  Log Message:
  -----------
  [RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.

Instead of zero extending the inputs by masking. We can shift them
left instead. This is cheaper when we don't zext.w instruction.

This does make the case where the inputs are already zero extended
or freely zero extendable worse though.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155530