[all-commits] [llvm/llvm-project] d53d84: [RISCV][AArch64][IRGen] Add a special case to Code...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d53d842d12ceb182f1f5c12cc001b09f9000dbf4
      https://github.com/llvm/llvm-project/commit/d53d842d12ceb182f1f5c12cc001b09f9000dbf4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-18 (Tue, 18 Jul 2023)

  Changed paths:
    M clang/lib/CodeGen/CGCall.cpp
    M clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c

  Log Message:
  -----------
  [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.

Before falling back to CreateCoercedStore, detect a scalable vector
return being coerced to fixed vector. Handle it using a vector.extract
intrinsic without going through memory.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D155495