[all-commits] [llvm/llvm-project] d5ab37: AMDGPU: Add baseline test for broken machine sinking
Matt Arsenault via All-commits
all-commits at lists.llvm.org
Tue Jul 18 03:16:04 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: d5ab379506252f4955c74841f1e12caa97317a57
https://github.com/llvm/llvm-project/commit/d5ab379506252f4955c74841f1e12caa97317a57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-07-18 (Tue, 18 Jul 2023)
Changed paths:
A llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
A llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
Log Message:
-----------
AMDGPU: Add baseline test for broken machine sinking
Commit: 3f8ef57bede94445b1a1042c987cc914a886e7ff
https://github.com/llvm/llvm-project/commit/3f8ef57bede94445b1a1042c987cc914a886e7ff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-07-18 (Tue, 18 Jul 2023)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir
Log Message:
-----------
MachineSink: Fix sinking VGPR def out of a divergent loop
This fixes sinking a VGPR def out of a loop past the reconvergence
point at the SI_END_CF. There was a prior fix which introduced
blockPrologueInterferes (D121277) to fix the same basic problem for
the post RA sink. This also had the special case isIgnorableUse case
which was incorrect, because in some contexts the exec use is not
ignorable.
I'm thinking about a new way to represent this which will avoid
needing hasIgnorableUse and isBasicBlockPrologue, which would function
more like the exception handling.
Fixes: SWDEV-407790
https://reviews.llvm.org/D155343
Compare: https://github.com/llvm/llvm-project/compare/7be7f232699f...3f8ef57bede9
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