[all-commits] [llvm/llvm-project] a64b3e: [RISCV] Re-define sha256, Zksed, and Zksh intrinsi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f
      https://github.com/llvm/llvm-project/commit/a64b3e92c7cb0dd474e0ecbdb9fb86c29487451f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-17 (Mon, 17 Jul 2023)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsRISCV.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c
    R clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksed.c
    R clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zksh.c
    M clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c
    R clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksed.c
    R clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zksh.c
    A clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c
    A clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/IR/AutoUpgrade.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
    M llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zksed-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv32zksh-intrinsic.ll
    A llvm/test/CodeGen/RISCV/rv64zknh-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
    A llvm/test/CodeGen/RISCV/rv64zksed-intrinsic-autoupgrade2.ll
    M llvm/test/CodeGen/RISCV/rv64zksed-intrinsic.ll
    A llvm/test/CodeGen/RISCV/rv64zksh-intrinsic-autoupgrade.ll
    M llvm/test/CodeGen/RISCV/rv64zksh-intrinsic.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll

  Log Message:
  -----------
  [RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

Previously we returned i32 on RV32 and i64 on RV64. The instructions
only consume 32 bits and only produce 32 bits. For RV64, the result
is sign extended to 64 bits like *W instructions.

This patch removes this detail from the interface to improve
portability and consistency. This matches the proposal for scalar
intrinsics here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44

I've included IR autoupgrade support as well.

I'll be doing this for other builtins/intrinsics that currently use
'long' in other patches.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D154647