[all-commits] [llvm/llvm-project] e9caa3: [DAG] Move lshr narrowing from visitANDLike to Sim...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e9caa37e9c69f6a6e5ab59d33b9d492054819ded
      https://github.com/llvm/llvm-project/commit/e9caa37e9c69f6a6e5ab59d33b9d492054819ded
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-17 (Mon, 17 Jul 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
    M llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
    M llvm/test/CodeGen/AMDGPU/shift-i128.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
    M llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
    M llvm/test/CodeGen/X86/3addr-or.ll
    M llvm/test/CodeGen/X86/and-shift.ll
    M llvm/test/CodeGen/X86/bswap.ll
    M llvm/test/CodeGen/X86/combine-bitreverse.ll
    M llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
    M llvm/test/CodeGen/X86/extract-bits.ll
    M llvm/test/CodeGen/X86/h-registers-0.ll
    M llvm/test/CodeGen/X86/lzcnt-cmp.ll
    M llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
    M llvm/test/CodeGen/X86/zext-lshr.ll

  Log Message:
  -----------
  [DAG] Move lshr narrowing from visitANDLike to SimplifyDemandedBits

Inspired by some of the cases from D145468

Let SimplifyDemandedBits handle the narrowing of lshr to half-width if we don't require the upper bits, the narrowed shift is profitable and the zext/trunc are free.

A future patch will propose the equivalent shl narrowing combine.

Differential Revision: https://reviews.llvm.org/D146121