[all-commits] [llvm/llvm-project] b7836d: [CodeGen]Allow targets to use target specific COPY...

Yashwant Singh via All-commits all-commits at lists.llvm.org
Fri Jul 7 10:00:17 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b7836d856206ec39509d42529f958c920368166b
  Author: Yashwant Singh <Yashwant.Singh at amd.com>
  Date:   2023-07-07 (Fri, 07 Jul 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LiveRangeEdit.cpp
    M llvm/lib/CodeGen/LiveRangeShrink.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/lib/CodeGen/SplitKit.h
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/test/CodeGen/Mips/madd-msub.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
    M llvm/test/CodeGen/X86/dagcombine-cse.ll
    M llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll

  Log Message:
  [CodeGen]Allow targets to use target specific COPY instructions for live range splitting

Replacing D143754. Right now the LiveRangeSplitting during register allocation uses
TargetOpcode::COPY instruction for splitting. For AMDGPU target that creates a
problem as we have both vector and scalar copies. Vector copies perform a copy over
a vector register but only on the lanes(threads) that are active. This is mostly sufficient
however we do run into cases when we have to copy the entire vector register and
not just active lane data. One major place where we need that is live range splitting.

Allowing targets to use their own copy instructions(if defined) will provide a lot of
flexibility and ease to lower these pseudo instructions to correct MIR.

- Introduce getTargetCopyOpcode() virtual function and use if to generate copy in Live range
- Replace necessary MI.isCopy() checks with TII.isCopyInstr() in register allocator pipeline.

Reviewed By: arsenm, cdevadas, kparzysz

Differential Revision: https://reviews.llvm.org/D150388

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