[all-commits] [llvm/llvm-project] 6f9080: [RISCV] Add a guard condition to orc_b/brev8 handl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f90808074c4241775e111d8aca61889b10d8d0a
      https://github.com/llvm/llvm-project/commit/6f90808074c4241775e111d8aca61889b10d8d0a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-07-07 (Fri, 07 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Add a guard condition to orc_b/brev8 handling in ReplaceNodeResults.

The orc_b and brev8 intrinsics are type overloaded, but only
i32 and XLen are supported types. The type legalization code in
ReplaceNodeResults only handles the i32 case on RV64. Add some
checks so we will fail type legalization for other types.