[all-commits] [llvm/llvm-project] 18013b: [RISCV] Add tests for unaligned segmented loads an...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18013bea468849d8be1b6a541a0cff0502877286
      https://github.com/llvm/llvm-project/commit/18013bea468849d8be1b6a541a0cff0502877286
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-07 (Fri, 07 Jul 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Add tests for unaligned segmented loads and stores

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D154535


  Commit: 02bb33c3ce7a83d47244ae16c8b4c625aba187a2
      https://github.com/llvm/llvm-project/commit/02bb33c3ce7a83d47244ae16c8b4c625aba187a2
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-07 (Fri, 07 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Check for alignment when lowering interleaved/deinterleaved loads/stores

As noted by @reames, we should be checking that the memory access is aligned to
the element size (or the unaligned vector memory access feature is enabled)
before lowering vlseg/vsseg intrinsics via the interleaved access pass.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D154536


Compare: https://github.com/llvm/llvm-project/compare/a7e13a99c2c6...02bb33c3ce7a