[all-commits] [llvm/llvm-project] 8ee1cc: AMDGPU: Fold out sign bit ops on frexp_exp

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8ee1cc82c9e54902a495204a537d2152b68ec757
      https://github.com/llvm/llvm-project/commit/8ee1cc82c9e54902a495204a537d2152b68ec757
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-07-06 (Thu, 06 Jul 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll

  Log Message:
  -----------
  AMDGPU: Fold out sign bit ops on frexp_exp

The sign bit has no impact on the exponent, so strip these away. Saves
on the source modifier encoding cost. I left the GlobalISel handling
until there's a resolution to issue #62628.

We should do this in instcombine too, but legalization should be
introducing more frexps than it currently is where this would occur.


  Commit: c70cae6315f30edc910f0fa46cfa39bc25051652
      https://github.com/llvm/llvm-project/commit/c70cae6315f30edc910f0fa46cfa39bc25051652
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-07-06 (Thu, 06 Jul 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

  Log Message:
  -----------
  AMDGPU: Make SIFixVGPRCopies preserve everything

All this does is add uses of reserved registers, which
aren't tracked by anything. Saves a loop info computation.


Compare: https://github.com/llvm/llvm-project/compare/90b83a6d6caa...c70cae6315f3