[all-commits] [llvm/llvm-project] 98aa84: [AMDGPU] Fix register class for a subreg in GCNRew...

[Valery via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 98aa8439f5e05cecdf232f303842be3c07d72547
      https://github.com/llvm/llvm-project/commit/98aa8439f5e05cecdf232f303842be3c07d72547
  Author: Valery Pykhtin <valery.pykhtin at gmail.com>
  Date:   2023-07-06 (Thu, 06 Jul 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

  Log Message:
  -----------
  [AMDGPU] Fix register class for a subreg in GCNRewritePartialRegUses.

1. Improved code that deduces register class from instruction definitions. Previously if some instruction didn't contain a reg class for an operand it was considered as no information on register class even if other instructions specified the class.

2. Added check on required size of resulting register because in some cases classes with smaller registers had been selected (for example VReg_1).

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D152832