[all-commits] [llvm/llvm-project] d91468: [RISCV] Add tests for stores of vector.interleave2

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d914686da25d4744fe5ebf565a8b4c0cd23016ce
      https://github.com/llvm/llvm-project/commit/d914686da25d4744fe5ebf565a8b4c0cd23016ce
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
    A llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Add tests for stores of vector.interleave2

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153863


  Commit: 70093fcf6c324da6f98a1e606afdaa9d04b5d1fd
      https://github.com/llvm/llvm-project/commit/70093fcf6c324da6f98a1e606afdaa9d04b5d1fd
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

  Log Message:
  -----------
  [RISCV] Lower interleave2 intrinsics to vsseg2

This patch teaches the RISCV TargetLowering class to lower interleave
intrinsics to vsseg2, so it can lower interleaved stores for scalable vectors.
Previously, we could only lower stores of interleaves for fixed length vectors
with vector shuffles.

This uses the lowerInterleaveIntrinsic interface for the interleaved
access pass that was added in D146218, and subsumes the DAG combine
approach taken in D144175

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D153864


  Commit: 86a9bbfdb3ee572fc5be084e0e5b2d2736346eba
      https://github.com/llvm/llvm-project/commit/86a9bbfdb3ee572fc5be084e0e5b2d2736346eba
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
    A llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

  Log Message:
  -----------
  [RISCV] Add tests for vector.deinterleave2s of loads

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D153875


  Commit: ea62fc79e7f95a73288e6d2402d30f91681849b6
      https://github.com/llvm/llvm-project/commit/ea62fc79e7f95a73288e6d2402d30f91681849b6
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-deinterleave-load.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

  Log Message:
  -----------
  [RISCV] Lower deinterleave2 intrinsics to vlseg2

Following from D153864, this patch implements the lowerDeinterleaveIntrinsic
hook to lower deinterleaves of loads into vlseg2 intrinsics.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153876


Compare: https://github.com/llvm/llvm-project/compare/cfbcbc8f88ed...ea62fc79e7f9