[all-commits] [llvm/llvm-project] a32d14: [X86] Fold BITOP(PACKSS(X, Z), PACKSS(Y, W)) --> PACK...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a32d14fd4c0a43c154f251df1ccfe57e8b0a711a
      https://github.com/llvm/llvm-project/commit/a32d14fd4c0a43c154f251df1ccfe57e8b0a711a
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
    M llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/cast-vsel.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
    M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll

  Log Message:
  -----------
  [X86] Fold BITOP(PACKSS(X,Z),PACKSS(Y,W)) --> PACKSS(BITOP(X,Y),BITOP(Z,W))

Fold allsignbits pack patterns to make better use of cheap (and commutable) logic ops


  Commit: 38721f29f8b33feefb13121e6d24dc54f345ae73
      https://github.com/llvm/llvm-project/commit/38721f29f8b33feefb13121e6d24dc54f345ae73
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
    M llvm/test/CodeGen/X86/vselect-packss.ll

  Log Message:
  -----------
  [X86] ComputeNumSignBitsForTargetNode - attempt to recognise PACKSSDW(PACKSSDW(X,Y),PACKSSDW(Z,W)) patterns

These are often used when we're packing vXi64 comparison results, but we don't have PACKSSQD so have to bitcast, which doesn't work well with num sign bits value tracking.


Compare: https://github.com/llvm/llvm-project/compare/7e486d5c2d26...38721f29f8b3