[all-commits] [llvm/llvm-project] 4e20ad: [X86] Remove unnecessary vzeroall/vzeroupper overr...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e20ad9470c27a4b4f3a5931c98264bfa014528d
      https://github.com/llvm/llvm-project/commit/4e20ad9470c27a4b4f3a5931c98264bfa014528d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td

  Log Message:
  -----------
  [X86] Remove unnecessary vzeroall/vzeroupper overrides from znver1/znver2 models

Noticed while trying to resurrect D138359 - the overrides matched the base class schedule WriteSystem/WriteMicrocoded definition (apart from znver2 where vzeroupper is almost free)


  Commit: ee72359c658f5e6759f9bbd2964bf5fc86e679ef
      https://github.com/llvm/llvm-project/commit/ee72359c658f5e6759f9bbd2964bf5fc86e679ef
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedAlderlakeP.td

  Log Message:
  -----------
  [X86] Remove unnecessary VPDPB/VPDPW overrides from AlderlakeP model

Noticed while trying to resurrect D138359 - the overrides matched the base class schedule WriteVecIMul definition


  Commit: c3b7ab728a7a1ee2ad4b638fafd477e533471d37
      https://github.com/llvm/llvm-project/commit/c3b7ab728a7a1ee2ad4b638fafd477e533471d37
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-07-05 (Wed, 05 Jul 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/independent-load-stores.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx1.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx2.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bw.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512bwvl.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512dq.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512dqvl.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vl.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-cmpxchg.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-f16c.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-mmx.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-movbe.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse1.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse2.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-sse41.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x87.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-xsave.s

  Log Message:
  -----------
  [X86] Fix Store AGU/Memory ports on IceLakeServer model

The IceLakeServer model was directly copied from SkylakeServer model and we didn't do much to adjust the changes in port layout etc.

IceLake handles all store AGU on ports 7/8 (and not 2/3/7 like Skylake), store memory ops are handled on ports 4/9 (and not just port 4)

Fixes #62602


Compare: https://github.com/llvm/llvm-project/compare/2dad496be353...c3b7ab728a7a