[all-commits] [llvm/llvm-project] f55d96: [DAG][AArch64] Handle vector types when expanding ...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f55d96b9a25d7ab00be542e657565dad9b8a3e7e
      https://github.com/llvm/llvm-project/commit/f55d96b9a25d7ab00be542e657565dad9b8a3e7e
  Author: David Green <david.green at arm.com>
  Date:   2023-07-02 (Sun, 02 Jul 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

  Log Message:
  -----------
  [DAG][AArch64] Handle vector types when expanding sdiv/udiv into mulh

The aarch64 backend will benefit from expanding 64vector sdiv/udiv into mulh
using shift(mul(ext, ext)), as the larger type size is legal and the mul(ext,
ext) can efficiently use smull/umull instructions. This extends the existing
code in GetMULHS to handle vector types for it.

Differential Revision: https://reviews.llvm.org/D154049