[all-commits] [llvm/llvm-project] 4f065f: [WebAssembly] Fix incorrect assertion in SIMD redu...

[Thomas Lively via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f065fcb5779a7bcdd02f00789ecc827c7a8e426
      https://github.com/llvm/llvm-project/commit/4f065fcb5779a7bcdd02f00789ecc827c7a8e426
  Author: Thomas Lively <tlively at google.com>
  Date:   2023-06-30 (Fri, 30 Jun 2023)

  Changed paths:
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll

  Log Message:
  -----------
  [WebAssembly] Fix incorrect assertion in SIMD reduction codegen

The codegen routine introduced in 18077e9fd688 did not account for vectors with
more than 16 lanes. Remove the incorrect assertion and bail out of the
optimization when encountering this case. Add test cases that previously
triggered the assertion. Unfortunately, these test cases now have terrible
codegen, but that is at least better than crashing.

Fixes #63500.

Differential Revision: https://reviews.llvm.org/D154124