[all-commits] [llvm/llvm-project] 9ad29e: [RISCV] Add fixed vector insert tests that are pas...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9ad29e7b3df4b6f8cb4e46d148855dd60c54f13f
      https://github.com/llvm/llvm-project/commit/9ad29e7b3df4b6f8cb4e46d148855dd60c54f13f
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-06-28 (Wed, 28 Jun 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

  Log Message:
  -----------
  [RISCV] Add fixed vector insert tests that are pass by value

So we can still test insert_vector_elt lowering with D152276

Reviewed By: frasercrmck, craig.topper

Differential Revision: https://reviews.llvm.org/D153964


  Commit: 742fb8b5c7036409f08ab0706f00057ac29ac773
      https://github.com/llvm/llvm-project/commit/742fb8b5c7036409f08ab0706f00057ac29ac773
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-06-28 (Wed, 28 Jun 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/vector-insert-shuffle-cycle.ll
    M llvm/test/CodeGen/ARM/fp16-promote.ll
    M llvm/test/CodeGen/ARM/vector-DAGCombine.ll
    M llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll
    M llvm/test/CodeGen/Mips/msa/basic_operations.ll
    M llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/X86/pr47874.ll
    M llvm/test/CodeGen/X86/pr59980.ll
    M llvm/test/CodeGen/X86/vec_insert-mmx.ll

  Log Message:
  -----------
  [DAGCombine] Fold (store (insert_elt (load p)) x p) -> (store x)

If we have a store of a load with no other uses in between it, it's
considered dead and is removed. So sometimes when legalizing a fixed
length vector store of an insert, we end up producing better code
through scalarization than without.
An example is the follow below:

  %a = load <4 x i64>, ptr %x
  %b = insertelement <4 x i64> %a, i64 %y, i32 2
  store <4 x i64> %b, ptr %x

If this is scalarized, then DAGCombine successfully removes 3 of the 4
stores which are considered dead, and on RISC-V we get:

  sd a1, 16(a0)

However if we make the vector type legal (-mattr=+v), then we lose the
optimisation because we don't scalarize it.

This patch attempts to recover the optimisation for vectors by
identifying patterns where we store a load with a single insert
inbetween, replacing it with a scalar store of the inserted element.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D152276


Compare: https://github.com/llvm/llvm-project/compare/a4521c25ae5c...742fb8b5c703